Attention has been paid to SiC as a material of a power device capable of obtaining high breakdown field strength. However, in a SiC trench gate MOSFET, breakdown field strength of SiC is so high that an electric field applied to a gate insulating film at a bottom of the trench is too high to realize a required life. Accordingly, an electric field at the bottom of the trench needs to be relaxed.
A structure having a p-type deep layer deeper than the bottom of the trench is proposed as a structure capable of relaxing an electric field at the bottom of the trench as above. By adopting such a structure, field concentration at the bottom of the trench can be relaxed by restricting an electric field from entering the bottom of the trench when the MOSFET is OFF. Consequently, breaking of the gate insulating film can be prevented.
However, an impurity hardly diffuses in SiC and it is difficult to provide a p-type deep layer over 1 μm deep by ion implantation and thermal diffusion of an impurity.
Non Patent Literature 1 discloses a method of providing a p-type deep layer of a great depth developed as an embedded epitaxial technique, by which a p-type layer is epitaxially grown to fill a trench. When the embedded epitaxial technique as above is used, a p-type deep layer over, for example, 1 μm deep can be formed by using neither ion implantation nor thermal diffusion of an impurity.
In a SiC semiconductor device, a p-type deep layer is provided in a cell region, and a p-type guard ring layer is provided in an outer peripheral region in which an outer peripheral breakdown voltage structure is formed to enclose an outer periphery of the cell region. Both of the p-type deep layer and the p-type guard ring layer can be provided by the embedded epitaxial technique.
However, a shape abnormality and surface irregularities are conformed with a p-type deep layer of a great depth and a p-type guard ring layer provided by the embedded epitaxial technique. For example, as is shown in FIG. 11A, a region where the layers are embedded expands due to a difference in width among trenches J1, or as is shown in FIG. 11B, a shape abnormality and surface irregularities occur at an intersection of two linear trenches J1.
When a trench gate formation process is performed later in presence of such irregularities, a desired gate shape cannot be obtained. Accordingly, leakage through the gate insulating film may occur and a required life cannot be realized due to a failure in sufficiently relaxing an electric field at the bottom of the trench. Because the p-type deep layer and the p-type guard ring layer are designed individually, a shape abnormality and irregularities on the surface readily occur particularly when the both layers are provided at a time.
Meanwhile, the surface may be planarized by grinding or polishing to remove surface irregularities. However, SiC is too hard to be processed with good control performance. It thus becomes necessary to planarize a surface of a p-type deep layer by improving patterns of trenches in which embedded epitaxy takes place.
The above has described a case where SiC is used as a semiconductor material. However, similar problems arise even when a p-type deep layer is provided by the embedded epitaxial technique using a semiconductor material other than SiC, for example, Si (silicon) or GaN (silicon nitride).